1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory, and more particularly, to a circuit for setting a severe, or rigorous, reference used in a program verification mode for determining whether or not data has been flawlessly written into a memory cell.
2. Description of the Related Art
In a conventional EPROM (ultraviolet erasable and programmable read only memory), differential sense amplifier 1, as shown in FIG. 3, is used to sense a potential, which is derived from the memory cell and set on a bit line. Sense amplifier 1 is connected to receive bit line potential VBL as a first input (comparison input), and reference potential VREF, from dummy cell circuit 30, as the other input (reference input).
Dummy cell circuit 30 is of substantially the same construction as memory cell (EPROM) circuit 2, and comprises a preset number of basic circuits, which are connected in parallel to attain a desired output level, and which include dummy cell 11, potential clamping MOS transistor 12, and load MOS transistor 13.
In this case, the gate of dummy cell 11 is connected to receive a "1" level voltage (ordinary power source voltage Vcc). Therefore, in the case of the above EPROM, the same reference input potential VREF for sense amplifier 1 is used in the ordinary readout operation and the program verification operation (which is a readout operation effected to verify the written-in contents immediately after the write-in operation).
An EPROM writer for externally writing data into the EPROM does so by utilizing a specified access manner. Therefore, even if correct readout data is obtained in the verification operation, the write amount (or degree of writing data) is not always sufficient, that is, data is not always written in perfect condition. In other words, it is not always ensured that a sufficiently large power source voltage margin can be obtained in an ordinary readout operation.